The present invention is related to field programmable integrated circuits, especially Field Programmable Gate Arrays (FPGAs), and more particularly, to floating gate MOS transistors used as switching elements in an FPGA.
Typically, an FPGA has an array of logic elements and wiring interconnections with thousands, or tens of thousands, of programmable interconnects so that the FPGA can be configured by the user into an integrated circuit with defined functions. Each programmable interconnect, or switch, can connect two circuit nodes in the integrated circuit to make (or break) a wiring interconnection or to set the function or functions of a logic element.
FPGAs use either memory cells or antifuses for the programmable interconnect. memory cells are reprogrammable and antifuses are programmable only once. A new non-volatile memory-type of programmable interconnect is disclosed in U.S. Pat. No. 5,764,096, entitled, "A GENERAL PURPOSE, NON-VOLATILE REPROGRAMMABLE SWITCH," issued Jun. 9, 1998 by Robert J. Lipp, Richard D. Freeman, Robert U. Broze, John M. Caywood, and Joseph G. Nolan, III, and assigned to the present assignee. In the FPGA described in the patent application, a non-volatile reprogrammable transistor memory (NVM) cell is used to provide a general purpose switching element to randomly interconnect FPGA wiring and circuit elements. Basically an NVM cell has an MOS transistor with a floating gate which may be charged and/or discharged. Charging and/or discharging the floating gate provides for the non-volatile programmability feature of NVM technologies.
In an FPGA, indeed, in any integrated circuit, it is important that the elements of the FPGA be as compact as possible for an efficient layout of the circuit and be as easily manufactured as possible. U.S. Pat. No. 5,633,518 by Robert U. Broze, for "Non-Volatile Reprogrammable Interconnect Cell With FN Tunneling and programming" and assigned to the present assignee is directed toward highly compact cells of one of the programmable interconnects described in U.S. Pat. No. 5,764,096, supra. An efficient array of such interconnects, each of which is selectively programmable, is achieved. Each programmable interconnect cell has a first MOS transistor having first and second source/drains connected to first and second circuit nodes respectively, and a floating gate for turning the first MOS transistor off and on responsive to the amount of charge on the gate. The cell also has a tunneling device with one terminal connected to the floating gate of the first MOS transistor and coupled to a programming/erase line through a tunneling oxide layer, a control gate capacitively coupled to the floating gate, and at least one tunneling control line for controllably inhibiting tunneling through the oxide layer. The tunneling control line and the programming/erase line form a PN junction which is close to, but laterally displaced from, the region below the tunneling oxide layer. Under a reverse bias, the charge of depletion region of the junction extends through the region below the tunneling oxide to block tunneling. This permits each programmable interconnect to be selectively programmable.
Our U.S. Pat. No. 5,838,040 is directed to an improved FPGA cell and array structure with improved manufacturing yield, reliability, programming speed, threshold margining, and cost. The cell includes a gate switch transistor and a gate sense transistor having common floating gates, the sense transistor also providing the programing and erasing of the switch transistor by Fowler-Nordheim (FN) electron tunneling to and from the transistor drain and the floating gate. In an array of cells or an FPGA tile, two column lines are respectively connected to the source and drain regions of the sense transistors in each column for use in sensing the threshold voltage of the sense transistor and switch transistor and thus measuring the programmed or erased state of the switch transistor.
Use of the sense transistor for programming and erasing of the switch transistor can impact the sensing function of the transistor. The sense and switch transistors should be identical devices for accurate sensing, tight distribution, and simple circuitry and fabrication steps. However, the programming and erasing function has heretofore required a non-symmetric drain junction in the sense transistor for electron tunneling between the floating gate and the drain. This asymmetry is difficult to scale down and can result in non-uniform FN programming (electron tunneling) and localized stress on the tunnel oxide. Further, the drain requires a longer channel length for preventing punch through, resulting in a larger cell height. The structure in U.S. Pat. No. 5,838,040 has a symmetrical source/drain structure with electron tunneling from both source/drain regions to the floating gate. However, the source/drains are formed by gate self-aligned implant which necessitates electron tunneling from the edge of the source/drain and the floating gate.
Other limitations are created by the fabrication of the programming drain/polysilicon gate structure. As illustrated in section view in FIG. 1, the control gate 110 and floating gate 112 of a sense/programming transistor in silicon substrate 113 must overlap the drain 114 more than the overlap of the source to facilitate electron tunneling between the drain 114 and floating gate 112. Due to the overlap the drain doping is not uniform since ion implant 118 extends under the gate structures by ion migration during annealing, as illustrated at 120. Further, the non-uniform polysilicon gate structure which has curved or smiling bottom surfaces at the gate edges affects the drain junction edge programming speed and requires a higher bitline voltage which results in increased bitline disturb and leakage.
The present invention is directed to an improvement in the FPGA cell and array disclosed in U.S. Pat. No. 5,838,040.